The VGA (video graphics array) analog monitor interconnect scheme has been adopted for use by virtually all personal computer (PC) systems in use today. Various efforts to replace this interconnect scheme have emerged and failed. The market continues to use this type of monitor interconnect because of its low-cost, ubiquity in the installed base, and its general ability to perform.
The existing VGA analog monitor interconnect scheme in wide use today transmits three analog display signals (R, G and B), two reference digital signals (HSYNC and VSYNC), and a few miscellaneous digital control signals. The common connector used on both ends of the standard interconnect cable is a 3 row 15 pin D-sub connector. Physical monitor interconnect performance limitations result in frequency dependent degradation, amplitude mismatches, delay mismatches, and crosstalk of the analog R, G and B signals. Such signal degradation and variability is generally tolerable for CRT and LCD monitors having a resolution in the range of up to 3 megapixels (400 MHz bandwidth). However, the demands on monitor interconnect performance have begun to rapidly increase as screen resolution has increased to beyond 3 megapixels. Existing standard monitor interconnect schemes are becoming a limiting factor with respect to efforts to provide enhanced computer user experiences and meeting increasing user expectations.
Previous proposals for achieving a higher level of interconnect performance use a different connector form factor (e.g., Molex Micro-cross), or use different electrical signaling (e.g., DVI uses digital signaling), that are not compatible with the huge installed base of analog 3 row 15 pin D-sub connectors (VGA). Such proposals have resulted in consumer confusion and frustration, market fragmentation and low adoption.
FIG. 1 depicts a conventional arrangement of a host computer 1 and display monitor 3. Interconnecting these components is a standard interconnect cable 5, in the case of the VGA connector standard, a cable equipped at the host computer end with an analog 3 row 15 pin D-sub connector.
FIG. 2 depicts a prior art display adapter 7, such as a VGA display adapter, included within conventional host computer 1. Display adapter 7 includes a graphics controller 9, which provides digital signals (display data 11, DAC BLANK signal 13, and DOT clock 15) to a Random Access Memory/Digital to Analog Converter (RAMDAC) 17, including in RAM a color look-up table. Data for each pixel of the display is transmitted synchronously with the DOT clock. RAMDAC 17 converts the received digital signals into digital color values using the color look-up table stored in RAM, and converts the digital color values to analog signals (red (R), green (G) and blue (B) signals 19, 21 and 23, respectively) for output to the display circuitry 25 of computer monitor 3 over associated signal lines of standard (e.g., VGA) interconnect 5. DAC Blank signal 13 causes RAMDAC 17 to suppress the R, G and B signals 19, 21 and 23 during horizontal and vertical blanking intervals, in synchronization with the display synch pulses HSYNCH 27 and VSYNCH 29. Display synch pulses HSYNC 112 and VSYNC 114 are provided by graphics controller 9 to the computer monitor directly, also over interconnect 5.
Computer monitor display circuitry 25 is configured to receive the analog R, G and B signals (19, 21 and 23, respectively) and HSYNC 25 and VSYNC 27 signals from host computer 1 and to utilize those signals for creating a corresponding display (e.g., in the case of a CRT monitor, through controlled activation and deflection of R, G and B scanning electron beam guns).
FIG. 3 is an illustrative representation of a scanning procedure for a CRT computer monitor 31. The path of an electron beam 33 (representative of three separate beams that would be provided, one for each of the R, G and B colors) sweeps across a phosphor coated screen in a horizontal line, beginning at the top left corner of the screen. Upon reaching the end of a horizontal line, a return trace or retrace 35 occurs, during which the R, G and B electron beams are blanked so that no image information is transmitted and no mark appears on the screen during the retrace. The electron beam then sweeps across the screen along the next horizontal line, followed by another horizontal retrace. Ultimately, the path of the electron beam moves along the bottom horizontal line of the screen, completing a full sweep of the screen, known as a field. (In the case of interlaced monitors, the electron beams scan only every other line within each field, filling in the skipped lines in a subsequent field.) The completion of each field is followed by a vertical retrace 37, during which the R, G and B electron beams are again blanked such that no image information is transmitted and no mark appears on the screen during the vertical retrace. The time period for horizontal retrace 35, during which the electron beams are also blanked, is known as the horizontal blanking interval. The time period for vertical retrace 37, during which the electron beams are blanked, is called the vertical blanking interval. The timing of the electron beam gun horizontal and vertical retraces (and the associated blanking intervals) are established in relation to horizontal and vertical synch pulses HSYNCH 27 and VSYNC 29, respectively.
LCD displays operate on different principals, not involving raster scanning or actual vertical or horizontal retraces. Instead, color LCD displays rely upon selective application of charges to cells of a liquid crystal panel utilizing a matrix of transistors, which in turn govern the extent to which red, green and blue components of light emanated from behind the computer's display panel are transmitted through the material of the liquid crystal panel at any given point (pixel). To retain compatibility with the huge installed base of the conventional analog VGA monitor interconnect, LCD display monitors generally accept analog input signals.
The usability of the standard VGA interconnect for high resolution monitor applications is limited by the usable bandwidth of the standard analog 3 row 15 pin D-sub VGA connection. Potential exists for increasing the usable bandwidth through improvements in the physical structure of the interconnect itself, e.g., improved shielding and impedance control, but these approaches have inherent constraints. The improvements obtainable are incremental and, in addition, physical improvements (even those that retain the 3 row 15 pin D-sub form factor), would require validation and adoption by suppliers. An approach with the potential for providing substantial gains in usable bandwidth of the VGA (and generally any other standard) interconnect form factor, not reliant on physical changes to the interconnect, would be highly desirable.